library verilog;
use verilog.vl_types.all;
entity control is
    generic(
        size_x          : integer := 320;
        size_y          : integer := 240;
        st_init         : vl_logic_vector(0 to 1) := (Hi0, Hi0);
        st_line_bl      : vl_logic_vector(0 to 1) := (Hi0, Hi1);
        st_line_valid   : vl_logic_vector(0 to 1) := (Hi1, Hi0);
        st_stop         : vl_logic_vector(0 to 1) := (Hi1, Hi1)
    );
    port(
        reset_n         : in     vl_logic;
        clk             : in     vl_logic;
        shutter         : in     vl_logic_vector(7 downto 0);
        Vldata          : out    vl_logic;
        Vrdata          : out    vl_logic;
        Vsample         : out    vl_logic;
        Vrsync          : out    vl_logic;
        Vlsync          : out    vl_logic;
        Vhdata          : out    vl_logic;
        Vhsync          : out    vl_logic;
        Vclamp          : out    vl_logic;
        frame           : out    vl_logic;
        line            : out    vl_logic;
        adcclk          : out    vl_logic;
        cdsclk1         : out    vl_logic;
        cdsclk2         : out    vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of size_x : constant is 1;
    attribute mti_svvh_generic_type of size_y : constant is 1;
    attribute mti_svvh_generic_type of st_init : constant is 1;
    attribute mti_svvh_generic_type of st_line_bl : constant is 1;
    attribute mti_svvh_generic_type of st_line_valid : constant is 1;
    attribute mti_svvh_generic_type of st_stop : constant is 1;
end control;
